USB2.0 PHY – Silicon Library Inc.
PCIe/USB/SATA PHY Appilcation example | Renesas
USB 3.0 PHY (Host/Device/OTG/Hub) - IP Solution - INNOSILICON
The Next-Generation Interconnect | Mouser
USB 2.0 extender control chipCH317 - NanjingQinhengMicroelectronics
DWTB: USB High Speed Inter-Chip (HSIC) IP: What is it? And why should I use it?
Archimago's Musings: MEASUREMENTS: Computer USB port noise, USB hubs and the 8kHz PHY Microframe Packet Noise
USBPHYC internal peripheral - stm32mpu
USB 2.0 PHY Verification
USB 3.0/2.0 Combo PHY IP for SoC Designs | Cadence IP
USB3250 | Microchip Technology
Soft Mixed Signal Corporation USB 2.0 PHY IP Cores
USB 2.0/HSIC PHY (Host/Device/OTG/Hub) - IP Solution - INNOSILICON
USB2.0 Soft IP: An Introduction to GOWIN Semiconductor's USB Solution for FPGA's - YouTube
Teledyne LeCroy - USB and USB Type-C® Electrical Test Solutions
USB2 PHY | Cadence
Figure 1 from Verilog synthesis of USB 2.0 full-speed device PHY IP | Semantic Scholar
USB 2.0 PHY IP Core
TUSB1210-Q1 data sheet, product information and support | TI.com
USB 2.0 OTG IP Core | Arasan Chip Systems
Mixed-Signal Verification for USB 2.0 Physical Layer IP
USB 2.0 Full High Speed Solution | NXP Semiconductors
USB 2.0 Full High Speed Solution | NXP Semiconductors
USB2 Controller | Cadence
USB 2.0 PHY IP Device/Host/OTG/Hub (Silicon proven in TSMC 40LP /LL)
HSIC USB 2.0 PHY IP
DWTB: USB High Speed Inter-Chip (HSIC) IP: What is it? And why should I use it?
